From eacbf5bb4d57af21c731f41251015d3b991ad490 Mon Sep 17 00:00:00 2001 From: guest Date: Fri, 30 Nov 2007 13:41:25 +0000 Subject: final version, initial import git-svn-id: svn+ssh://mecka.net/home/svn/rtcorba-thesis@1 cba7306a-a4a0-4afd-bcb4-bd19f8a24309 --- tmp/diplomathesis.lof | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100755 tmp/diplomathesis.lof (limited to 'tmp/diplomathesis.lof') diff --git a/tmp/diplomathesis.lof b/tmp/diplomathesis.lof new file mode 100755 index 0000000..170c262 --- /dev/null +++ b/tmp/diplomathesis.lof @@ -0,0 +1,43 @@ +\contentsline {figure}{\numberline {1}{\ignorespaces embedded System (Quelle: http://www.acmesystems.it)}}{13}{figure.1} +\contentsline {figure}{\numberline {2}{\ignorespaces verteiltes System}}{14}{figure.2} +\contentsline {figure}{\numberline {3}{\ignorespaces }}{14}{figure.3} +\contentsline {figure}{\numberline {4}{\ignorespaces }}{15}{figure.4} +\contentsline {figure}{\numberline {5}{\ignorespaces }}{16}{figure.5} +\contentsline {figure}{\numberline {6}{\ignorespaces ORB mit Schnittstellen zu Applikation und System}}{16}{figure.6} +\contentsline {figure}{\numberline {7}{\ignorespaces Realtime CORBA Erweiterungen (Quelle: \cite {rtcorbaspec})}}{20}{figure.7} +\contentsline {figure}{\numberline {8}{\ignorespaces Versuchsaufbau f\"ur Latenzmessungen}}{25}{figure.8} +\contentsline {figure}{\numberline {9}{\ignorespaces Struktur des ACE Frameworks (Quelle: http://www.cs.wustl.edu/\nobreakspace {}schmidt/)}}{26}{figure.9} +\contentsline {figure}{\numberline {10}{\ignorespaces }}{28}{figure.10} +\contentsline {figure}{\numberline {11}{\ignorespaces Sequenzdiagramm: V1 Prozessabbild \"ubertragen}}{31}{figure.11} +\contentsline {figure}{\numberline {12}{\ignorespaces Datenflu\ss : V1 Prozessabbild via TAO \"ubertragen}}{32}{figure.12} +\contentsline {figure}{\numberline {13}{\ignorespaces Latenzzeiten bei varriierender Systembelastung}}{34}{figure.13} +\contentsline {figure}{\numberline {14}{\ignorespaces Receiver u. Supplier o. zus\"atzl. Systemlast}}{35}{figure.14} +\contentsline {figure}{\numberline {15}{\ignorespaces Receiver o. zus\"atzl. Systemlast; Supplier mit CPU Last}}{35}{figure.15} +\contentsline {figure}{\numberline {16}{\ignorespaces Receiver o. zus\"atzl. Systemlast; Supplier m. CPU, Netz u. HD Last}}{35}{figure.16} +\contentsline {figure}{\numberline {17}{\ignorespaces Receiver m. Netzlast; Supplier o. zus\"atzl. Last}}{35}{figure.17} +\contentsline {figure}{\numberline {18}{\ignorespaces Receiver u. Supplier m. CPU, Netz u. HD Last}}{36}{figure.18} +\contentsline {figure}{\numberline {19}{\ignorespaces Receiver m. CPU u. HD Last; Supplier m. CPU, Netz u. HD Last}}{36}{figure.19} +\contentsline {figure}{\numberline {20}{\ignorespaces Supplier u. Receiver o. Last}}{38}{figure.20} +\contentsline {figure}{\numberline {21}{\ignorespaces Supplier u. Receiver m. xdd, flood ping u. cpuburnP5 belastet}}{38}{figure.21} +\contentsline {figure}{\numberline {22}{\ignorespaces Sequenzdiagramm V2}}{39}{figure.22} +\contentsline {figure}{\numberline {23}{\ignorespaces CPX1 u. 2 o. Last}}{40}{figure.23} +\contentsline {figure}{\numberline {24}{\ignorespaces CPX1 u. 2 m. xdd, flood ping u. cpuburnP5 belastet}}{40}{figure.24} +\contentsline {figure}{\numberline {25}{\ignorespaces RT EventService mit 2 Consumern}}{41}{figure.25} +\contentsline {figure}{\numberline {26}{\ignorespaces Abh\"angigkeit Datenmenge - Latenz}}{41}{figure.26} +\contentsline {figure}{\numberline {27}{\ignorespaces 3 CPXen verbunden mit QoS-Switch}}{42}{figure.27} +\contentsline {figure}{\numberline {28}{\ignorespaces wireshark dump: \"Ubertragung einer niedrig priorisierten Logdatei}}{44}{figure.28} +\contentsline {figure}{\numberline {29}{\ignorespaces wireshark dump: \"Ubertragung eines Prozessabbilds mit h\"ochster RTCORBA Priorit\"at}}{44}{figure.29} +\contentsline {figure}{\numberline {30}{\ignorespaces wireshark dump: entsprechend der RTCORBA Priorit\"at wird auch die diffServ Priorit\"at gesetzt}}{44}{figure.30} +\contentsline {figure}{\numberline {31}{\ignorespaces V5 immediate case}}{45}{figure.31} +\contentsline {figure}{\numberline {32}{\ignorespaces V5 worst case}}{45}{figure.32} +\contentsline {figure}{\numberline {33}{\ignorespaces V5 immediate case mit Cisco Switch}}{46}{figure.33} +\contentsline {figure}{\numberline {34}{\ignorespaces Foto: Versuchsaufbau V5 mit Cisco Switch}}{47}{figure.34} +\contentsline {figure}{\numberline {35}{\ignorespaces UML Klassendiagramm Zugriff auf digitale Ein- und Ausg\"ange}}{54}{figure.35} +\contentsline {figure}{\numberline {36}{\ignorespaces UML Klassendiagramm C\#\ - C++ Demoapplikation}}{63}{figure.36} +\contentsline {figure}{\numberline {37}{\ignorespaces Bedienoberfl\"ache}}{66}{figure.37} +\contentsline {figure}{\numberline {38}{\ignorespaces Schema Prozess\"uberwachung}}{80}{figure.38} +\wisecftsetpnumwidth {4em} \wisecftsetrmarg {5em} +\contentsline {figure}{\numberline {39}{\ignorespaces CPX, embedded System zur Steuerung der TRUMPF Festk\"orperlaser}}{XVII}{figure.39} +\contentsline {figure}{\numberline {40}{\ignorespaces Bedienpanel zur Steuerung der TRUMPF Festk\"orperlaser}}{XVIII}{figure.40} +\contentsline {figure}{\numberline {41}{\ignorespaces Screenshot: latencyTest}}{XIX}{figure.41} +\wisecftsetpnumwidth {1.55em} \wisecftsetrmarg {2.55em} -- cgit v1.2.3