diff options
| -rw-r--r-- | basics/Makefile | 6 | ||||
| -rw-r--r-- | basics/cpu-arch/Makefile | 9 | ||||
| -rw-r--r-- | basics/cpu-arch/hints_cpu-arch_de.tex | 15 | ||||
| -rw-r--r-- | basics/cpu-arch/pres_cpu-arch.tex | 285 | ||||
| -rw-r--r-- | basics/section.tex | 3 | ||||
| -rw-r--r-- | configpres.tex | 4 | ||||
| -rw-r--r-- | images/caches.dia | bin | 0 -> 2379 bytes | |||
| -rw-r--r-- | images/caches.png | bin | 0 -> 5870 bytes | |||
| -rw-r--r-- | images/fcse.dia | bin | 0 -> 1175 bytes | |||
| -rw-r--r-- | images/fcse.png | bin | 0 -> 4187 bytes |
10 files changed, 320 insertions, 2 deletions
diff --git a/basics/Makefile b/basics/Makefile new file mode 100644 index 0000000..c0c47ad --- /dev/null +++ b/basics/Makefile @@ -0,0 +1,6 @@ +SUBDIRS = `ls -1 | grep -v *.tex | grep -v Makefile` + +all clean:: + for dir in $(SUBDIRS) ; do \ + (cd $$dir && make $@); \ + done diff --git a/basics/cpu-arch/Makefile b/basics/cpu-arch/Makefile new file mode 100644 index 0000000..d641258 --- /dev/null +++ b/basics/cpu-arch/Makefile @@ -0,0 +1,9 @@ +all: + for pdf in `ls -1 *.tex` ; do \ + TEXINPUTS=`pwd`/../..:.:..:$(TEXINPUTS) pdflatex $$pdf; \ + TEXINPUTS=`pwd`/../..:.:..:$(TEXINPUTS) pdflatex $$pdf; \ + done + +clean: + rm -f *.aux *.log *.pdf *.log *.snm *.toc *.vrb *.nav *.out + diff --git a/basics/cpu-arch/hints_cpu-arch_de.tex b/basics/cpu-arch/hints_cpu-arch_de.tex new file mode 100644 index 0000000..62ddc81 --- /dev/null +++ b/basics/cpu-arch/hints_cpu-arch_de.tex @@ -0,0 +1,15 @@ +\documentclass{article} +\usepackage{german} +\usepackage[utf8]{inputenc} + +\begin{document} + +\section{CPU Architekturen} + +\subsection{Lernziele} +\begin{itemize} +\item Was bedeutet 8, 16, 32, \dots bit ? +\item Bedeutung MMU / keine MMU und Linux? +\item ARM, PowerPC / CELL, x86 +\end{itemize} +\end{document} diff --git a/basics/cpu-arch/pres_cpu-arch.tex b/basics/cpu-arch/pres_cpu-arch.tex new file mode 100644 index 0000000..cbbada3 --- /dev/null +++ b/basics/cpu-arch/pres_cpu-arch.tex @@ -0,0 +1,285 @@ +\input{configpres} + +\subsection{Prozessor Architekturen} + +\title{\lq Prozessor Architekturen\rq} +\maketitle + +\begin{frame} +\frametitle{Übersicht} +\tableofcontents +\end{frame} + +\subsubsection{Prozessoren} +\begin{frame} +\frametitle{Aufbau} +Register - Rechenwerk - Befehlsdekoder - Bus - Cache (optional) + +\begin{description} +\item[Register] Konfiguration, Zwischenspeicher, Operanden, Stack, I/O +\item[Rechenwerk] mind. eine ALU (Arithmetic Logical Unit: ADD, NOT, AND, \dots) +\end{description} +\end{frame} + +\begin{frame} +\frametitle{Aufbau} +Register - Rechenwerk - Befehlsdekoder - Bus - Cache (optional) + +\begin{description} +\item[Befehlsdekoder] + \begin{itemize} + \item FETCH - Befehl (OPCODE) aus RAM / ROM laden + (Prefetch - laden mehrere Befehle in ein Prefetch Register) + \item DECODE - OPCODE in ALU-Schaltinstruktionen wandeln + \item FETCH - Operanden (OPERANDS) aus RAM / ROM laden + \item EXECUTE + \item WRITE BACK - schreiben des Ergebnises in RAM / ROM (OPCOUNTER++) + \end{itemize} +\item[Bus] Adressbus (zentraler Adressdecoder -> Chip Select), Datenbus +\end{description} +\end{frame} + +\begin{frame} +\frametitle{Aufbau} +Register - Rechenwerk - Befehlsdekoder - Bus - Cache (optional) + +\begin{description} +\item[Cache] beinhaltet zuletzt verwendete Daten + \begin{itemize} + \item L1 im Kern / wenige KB gross / am Schnellsten abrufbar + \item L2 nicht im Kern / wenige MB gross + \item L3 von allen Kernen geteilt / einige MB gross + \end{itemize} +\end{description} +\end{frame} + +\subsubsection{OPCODE vs Assembler} +\begin{frame}[containsverbatim] +\frametitle{OPCODE vs Assembler} +\begin{description} +\item[OPCODES] sind immer Prozessorspezifisch +\item[OPCODE] eindeutige Nummer eines Befehls +\item[Befehlssatz] Summe aller OPCODES eines Prozessors +\item[Mnemonic] lesbare Abk. eines OPCODES -> Assemblerbefehl +\end{description} + +Beispiel 8086: +\begin{verbatim} +OPCODE: 0130 +Mnemonic: INC +SI (Sourceindexregister) wird um den Wert eins inkrementiert. +\end{verbatim} +\end{frame} + +\begin{frame} +\frametitle{Aufgabe} +\begin{itemize} +\item Schreiben Sie ein sehr einfaches C Programm +\item Disassemblen Sie das Programm +\item Betrachten Sie das Programm in einem HEX Editor und versuchen Sie die OPCODES zu finden +\end{itemize} +\end{frame} + +\begin{frame}[containsverbatim] +\frametitle{Disassemble} +\begin{verbatim} +simple.c: +int main(int argc, char **argv) +{ + return argc++; +} + +$ gcc -o simple.c +\end{verbatim} +\end{frame} + +\begin{frame}[containsverbatim] +\frametitle{Disassemble} +\begin{verbatim} +$ objdump -d a.out + +00000000004004b4 <main>: + 4004b4: 55 push %rbp + 4004b5: 48 89 e5 mov %rsp,%rbp + 4004b8: 89 7d fc mov %edi,-0x4(%rbp) + 4004bb: 48 89 75 f0 mov %rsi,-0x10(%rbp) + 4004bf: 8b 45 fc mov -0x4(%rbp),%eax + 4004c2: 83 45 fc 01 addl $0x1,-0x4(%rbp) + 4004c6: c9 leaveq + 4004c7: c3 retq + 4004c8: 90 nop + 4004c9: 90 nop + 4004ca: 90 nop + 4004cb: 90 nop + 4004cc: 90 nop + 4004cd: 90 nop + 4004ce: 90 nop + 4004cf: 90 nop +\end{verbatim} +\end{frame} + +\begin{frame}[containsverbatim] +\frametitle{Disassemble} +\begin{verbatim} +$ hexdump a.out | less + +00004b0 c3c9 9090 4855 e589 7d89 48fc 7589 8bf0 +00004c0 fc45 4583 01fc c3c9 9090 9090 9090 9090 +00004d0 c3f3 0ceb 9090 9090 9090 9090 9090 9090 +00004e0 8948 246c 4cd8 6489 e024 8d48 332d 2009 +00004f0 4c00 258d 092c 0020 894c 246c 4ce8 7489 +0000500 f024 894c 247c 48f8 5c89 d024 8348 38ec +\end{verbatim} +\end{frame} + +\subsubsection{8, 16, 32, \dots bit?} +\begin{frame} +\frametitle{n-Bit-Architektur} +Pro Takt werden max. n-Bit Daten verarbeitet. + +Hieraus leitet sich i.d.R. auch die Breite der internen Register, sowie des +Adress- und des Datenbusses ab. + +Vorteil: Adressraum / Datenbreite +Nachteil: Speicherbedarf Pointer +\end{frame} + +\subsubsection{Memory Management Unit} + +\begin{frame} +\frametitle{Memory Managemenut Unit (MMU)} +\begin{itemize} +\item Prozess sieht zusammenh\"angenden, konstanten, virtuellen Speicher +\item Kernel programmiert den TLB (Translation Look-aside Buffer) der MMU +\item Speicherzugriff auf virtuelle Adresse wird von der MMU in tats\"achliche, + physikalische Adresse \"ubersetzt +\end{itemize} +\end{frame} + +\subsubsection{ARM, PowerPC / CELL, x86} + +\begin{frame} +\frametitle{ARM - Advanced RISC Machines Ltd.} +\begin{itemize} +\item erstellt CPU Design +\item ARM Architektur: +\begin{itemize} +\item Handy, Smartphone, Nintendo DS, iPad, \dots +\item RISC - schlanker, effizienter Befehlssatz +\item LE / BE umschaltbar +\end{itemize} +\end{itemize} +\end{frame} + +\begin{frame} +\frametitle{ARM: ARM9} +\begin{itemize} +\item 32-bit RISC CPU design +\item ARM9T (based on ARMv4T) +\item ARM9E (based on ARMv5TE, longer pipelines, enhanced instruction set) +\end{itemize} +\end{frame} + +\subsection{ARM: Xscale} +\begin{frame} +\frametitle{Xscale} +\begin{itemize} +\item Xscale is Marvell's implementation of the ARMv5 architecture +\item The Xscale family consists of five different families: +\begin{itemize} +\item IXP (network processors) +\item IXC (control plane processors) +\item IOP (i/o processors) +\item PXA (application processors) +\item CE (consumer electronics processors) +\end{itemize} +\end{itemize} +\end{frame} + +\begin{frame} +\frametitle{ARM: ARM9 - Caches} +\begin{itemize} +\item V irtually I ndexed, V irtually T agged (VIVT) +\end{itemize} +\end{frame} + +\begin{frame} +\frametitle{ARM: Caches} +\begin{figure}[h] +\centering +\includegraphics[width=11cm]{images/caches.png} +\label{img:caches} +\end{figure} +\end{frame} + +\begin{frame} +\frametitle{ARM: ARM9 - Caches: Latency drawbacks} +\begin{itemize} +\item BUT: On Linux each process has its own virtual address space. +\pause +\item VIVT leads to a more frequent cache flushing +\pause +\item The cost of the cache flushing is about 1k - 18k CPU cycles +\pause +\item ''indirect cost'' up to 50k CPU cycles\\ +(200us on a 250MHz CPU!!) +\end{itemize} +\end{frame} + +\begin{frame} +\frametitle{ARM: ARM9 - Fast Context Switching Extension} +\begin{figure}[h] +\centering +\includegraphics[width=11cm]{images/fcse.png} +\label{img:fcse} +\end{figure} +\pause +\begin{itemize} +\item The first 32MB of the address space are augmented with the contents of the 7 bit +PID register. +\pause +\item This leads to 128 x 32MB address spaces +\end{itemize} +\end{frame} + +\begin{frame} +\frametitle{ARM: ARM11} +\begin{itemize} +\item V irtually I ndexed, P hysically T agged caches (VIPT) +\item High performance memory system +\item Designed to run at high CPU frequencies +\end{itemize} +\end{frame} + +\begin{frame} +\frametitle{ARM: Cortex - The new generation of ARM CPUs} +Splitted into three families: +\begin{itemize} +\item Cortex A: Application (variable caches, MMU / MPU) +\item Cortex M: Microcontroller (no cache, MPU optional) +\item Cortex R: Realtime (variable cache, MPU optional) +\end{itemize} +\end{frame} + +\begin{frame} +\frametitle{PowerPC} +\end{frame} + +\begin{frame} +\frametitle{CELL} +\end{frame} + +\begin{frame} +\frametitle{x86} +\end{frame} + +\subsubsection{Voraussetzungen f\"ur Linux} +\begin{frame} +Bit ? + +MMU ? + +ARCH Support ? +\end{frame} + +\input{tailpres} diff --git a/basics/section.tex b/basics/section.tex new file mode 100644 index 0000000..547ad23 --- /dev/null +++ b/basics/section.tex @@ -0,0 +1,3 @@ +\section{verschiedene Grundlagen} + +%In diesem Kapitel werden Grundlagen behandelt, welche nicht direkt mit Linux zu tun haben, aber f\"ur ein allgemeines Verst\"andnis notwendig sind. diff --git a/configpres.tex b/configpres.tex index c8f0c5d..6417db2 100644 --- a/configpres.tex +++ b/configpres.tex @@ -1,7 +1,7 @@ \documentclass{beamer} \mode<presentation> { - \usetheme{linutronix} + \usetheme{Dresden} } \usepackage{german} \usepackage[utf8]{inputenc} @@ -11,7 +11,7 @@ \usepackage{graphicx} \usepackage{lxextras} -\institute{Linutronix GmbH} +\author{Manuel Traut} \definecolor{lbcolor}{RGB}{255,210,150} \lstset{ language=C++, diff --git a/images/caches.dia b/images/caches.dia Binary files differnew file mode 100644 index 0000000..a990772 --- /dev/null +++ b/images/caches.dia diff --git a/images/caches.png b/images/caches.png Binary files differnew file mode 100644 index 0000000..37d266a --- /dev/null +++ b/images/caches.png diff --git a/images/fcse.dia b/images/fcse.dia Binary files differnew file mode 100644 index 0000000..418be7d --- /dev/null +++ b/images/fcse.dia diff --git a/images/fcse.png b/images/fcse.png Binary files differnew file mode 100644 index 0000000..85d6997 --- /dev/null +++ b/images/fcse.png |
