From a67b9e7e770e921a021e22deec3d1f6c24b0c6df Mon Sep 17 00:00:00 2001
From: Manuel Traut <manut@mecka.net>
Date: Wed, 9 Feb 2011 01:28:15 +0100
Subject: update basics/cpu-arch

- thx to jan, for the arm arch slides
- short mmu introduction

Signed-off-by: Manuel Traut <manut@mecka.net>
---
 basics/cpu-arch/pres_cpu-arch.tex | 122 ++++++++++++++++++++++++++++++++++++--
 1 file changed, 117 insertions(+), 5 deletions(-)

(limited to 'basics/cpu-arch/pres_cpu-arch.tex')

diff --git a/basics/cpu-arch/pres_cpu-arch.tex b/basics/cpu-arch/pres_cpu-arch.tex
index 70f2bcc..cbbada3 100644
--- a/basics/cpu-arch/pres_cpu-arch.tex
+++ b/basics/cpu-arch/pres_cpu-arch.tex
@@ -149,16 +149,128 @@ Nachteil: Speicherbedarf Pointer
 \begin{frame}
 \frametitle{Memory Managemenut Unit (MMU)}
 \begin{itemize}
-\item blurb 
+\item Prozess sieht zusammenh\"angenden, konstanten, virtuellen Speicher
+\item Kernel programmiert den TLB (Translation Look-aside Buffer) der MMU
+\item Speicherzugriff auf virtuelle Adresse wird von der MMU in tats\"achliche,
+	physikalische Adresse \"ubersetzt
 \end{itemize}
 \end{frame}
 
 \subsubsection{ARM, PowerPC / CELL, x86}
+
+\begin{frame}
+\frametitle{ARM - Advanced RISC Machines Ltd.}
+\begin{itemize}
+\item erstellt CPU Design
+\item ARM Architektur:
+\begin{itemize}
+\item Handy, Smartphone, Nintendo DS, iPad, \dots
+\item RISC - schlanker, effizienter Befehlssatz
+\item LE / BE umschaltbar
+\end{itemize}
+\end{itemize}
+\end{frame}
+
+\begin{frame}
+\frametitle{ARM: ARM9}
+\begin{itemize}
+\item 32-bit RISC CPU design
+\item ARM9T (based on ARMv4T)
+\item ARM9E (based on ARMv5TE, longer pipelines, enhanced instruction set)
+\end{itemize}
+\end{frame}
+
+\subsection{ARM: Xscale}
+\begin{frame}
+\frametitle{Xscale}
+\begin{itemize}
+\item Xscale is Marvell's implementation of the ARMv5 architecture
+\item The Xscale family consists of five different families:
+\begin{itemize}
+\item IXP (network processors)
+\item IXC (control plane processors)
+\item IOP (i/o processors)
+\item PXA (application processors)
+\item CE (consumer electronics processors)
+\end{itemize}
+\end{itemize}
+\end{frame}
+
+\begin{frame}
+\frametitle{ARM: ARM9 - Caches}
+\begin{itemize}
+\item V irtually I ndexed, V irtually T agged (VIVT)
+\end{itemize}
+\end{frame}
+
+\begin{frame}
+\frametitle{ARM: Caches}
+\begin{figure}[h]
+\centering
+\includegraphics[width=11cm]{images/caches.png}
+\label{img:caches}
+\end{figure}
+\end{frame}
+
+\begin{frame}
+\frametitle{ARM: ARM9 - Caches: Latency drawbacks}
+\begin{itemize}
+\item BUT: On Linux each process has its own virtual address space.
+\pause
+\item VIVT leads to a more frequent cache flushing
+\pause
+\item The cost of the cache flushing is about 1k - 18k CPU cycles
+\pause
+\item ''indirect cost'' up to 50k CPU cycles\\
+(200us on a 250MHz CPU!!)
+\end{itemize}
+\end{frame}
+
+\begin{frame}
+\frametitle{ARM: ARM9 - Fast Context Switching Extension}
+\begin{figure}[h]
+\centering
+\includegraphics[width=11cm]{images/fcse.png}
+\label{img:fcse}
+\end{figure}
+\pause
+\begin{itemize}
+\item The first 32MB of the address space are augmented with the contents of the 7 bit
+PID register.
+\pause
+\item This leads to 128 x 32MB address spaces
+\end{itemize}
+\end{frame}
+
+\begin{frame}
+\frametitle{ARM: ARM11}
+\begin{itemize}
+\item V irtually I ndexed, P hysically T agged caches (VIPT)
+\item High performance memory system
+\item Designed to run at high CPU frequencies
+\end{itemize}
+\end{frame}
+
+\begin{frame}
+\frametitle{ARM: Cortex - The new generation of ARM CPUs}
+Splitted into three families:
+\begin{itemize}
+\item Cortex A: Application (variable caches, MMU / MPU)
+\item Cortex M: Microcontroller (no cache, MPU optional)
+\item Cortex R: Realtime (variable cache, MPU optional)
+\end{itemize}
+\end{frame}
+
+\begin{frame}
+\frametitle{PowerPC}
+\end{frame}
+
+\begin{frame}
+\frametitle{CELL}
+\end{frame}
+
 \begin{frame}
-\frametitle{ARM}
-\begin{enumerate}
-\item v1
-\end{enumerate}
+\frametitle{x86}
 \end{frame}
 
 \subsubsection{Voraussetzungen f\"ur Linux}
-- 
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